 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| M24256-B M24128-B 256Kbit and 128Kbit Serial IC Bus EEPROM With Three Chip Enable Lines FEATURES SUMMARY Compatible with I2C Extended Addressing Two Wire I2C Serial Interface Supports 400kHz Protocol Single Supply Voltage: - 4.5 to 5.5V for M24xxx-B - 2.5 to 3.6V for M24xxx-BV - 2.5 to 5.5V for M24xxx-BW - 1.8 to 5.5V for M24xxx-BR - 1.8 to 3.6V for M24xxx-BS Hardware Write Control BYTE and PAGE WRITE (up to 64 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than 100,000 Erase/Write Cycles - More than 1 Million Erase/Write cycles for the products specified in Table 26. More than 40 Year Data Retention Figure 1. Packages 8 1 PDIP8 (BN) 8 1 SO8 (MN) 150 mil width 8 1 SO8 (MW) 200 mil width TSSOP8 (DW) 169 mil width April 2004 1/27 M24256-B, M24128-B TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus . . . . . . . . . . . . . . . 5 Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/27 M24256-B, M24128-B DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. Operating Conditions (M24xxx-B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8. Operating Conditions (M24xxx-BV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Operating Conditions (M24xxx-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10. Operating Conditions (M24128-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 11. Operating Conditions (M24256-BS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 12. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 13. Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 14. M24xxx-BV Power-Up Timing and Vth Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 15. DC Characteristics (M24xxx-B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 16. DC Characteristics (M24xxx-BV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 17. DC Characteristics (M24xxx-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 18. DC Characteristics (M24128-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 19. DC Characteristics (M24256-BS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 20. AC Characteristics (M24xxx-B, M24xxx-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 21. AC Characteristics (M24xxx-BV, M24128-BR, M24256-BS) . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12.PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 21 Table 22. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 21 Figure 13.SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 22 Table 23. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 22 Figure 14.SO8 wide - 8 lead Plastic Small Outline, 200 mils body width, Package Outline . . . . . . 23 Table 24. SO8 wide - 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data 23 Figure 15.TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 24 Table 25. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 24 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 27. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3/27 M24256-B, M24128-B SUMMARY DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are organized as 32K x 8 bits (M24256-B) and 16K x 8 bits (M24128-B). Figure 2. Logic Diagram VCC I 2C-compatible 3 E0-E2 SCL WC M24256-B M24128-B SDA VSS AI02809 Table 1. Signal Names E0, E1, E2 SDA SCL WC VCC VSS Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Power On Reset: VCC Lock-Out Write Protect In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. At Power-up, the internal reset is held active until VCC has reached the POR threshold value, and all operations are disabled - the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid V CC must be applied before applying any logic signal. When the power supply is turned on, V CC rises from VSS to VCC(min), passing through a value Vth in between. The -V and -S versions of the device, the M24xxx-BV and M24xxx-BS, ignore all instructions until a time delay of tPU has elapsed after the moment that V CC rises above the Vth threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No instructions should be sent until the later of: - tPU after VCC passed the Vth threshold - VCC passed the VCC(min) level These values are specified in Table 14.. Figure 3. DIP, SO and TSSOP Connections M24256-B M24128-B E0 E1 E2 VSS 1 2 3 4 8 7 6 5 AI02810B I2C uses a two wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I 2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW bit (as described in Table 2.), terminated by an acknowledge bit. VCC WC SCL SDA Note: See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1. 4/27 M24256-B, M24128-B SIGNAL DESCRIPTION Serial Clock (SCL). This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V CC. (Figure 4. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA). This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4. indicates how the value of the pull-up resistor can be calculated). Chip Enable (E0, E1, E2). These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7bit Device Select Code. These inputs must be tied to V CC or VSS, to establish the Device Select Code. When not connected (left floating), these inputs are read as Low (0,0,0). Write Control (WC). This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF) AI01665 RL SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS CBUS 1000 5/27 M24256-B, M24128-B Figure 5. I2C Bus Protocol SCL SDA SDA Input SDA Change START Condition STOP Condition SCL 1 2 3 7 8 9 SDA MSB ACK START Condition SCL 1 2 3 7 8 9 SDA MSB ACK STOP Condition AI00792B Table 2. Device Select Code Device Type Identifier1 b7 Device Select Code 1 b6 0 b5 1 b4 0 Chip Enable Address2 b3 E2 b2 E1 b1 E0 RW b0 RW Note: 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. Table 3. Most Significant Byte b15 b14 b13 b12 b11 b10 b9 b8 Table 4. Least Significant Byte b7 b6 b5 b4 b3 b2 b1 b0 6/27 M24256-B, M24128-B DEVICE OPERATION The device supports the I2C protocol. This is summarized in Figure 5.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24xxx-B device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 2. (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode. Table 5. Operating Modes Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write Note: 1. X = VIH or VIL. RW bit 1 0 WC 1 X X Bytes 1 1 Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address reSTART, Device Select, RW = 1 X X VIL VIL 1 0 0 1 1 Similar to Current or Random Address Read START, Device Select, RW = 0 START, Device Select, RW = 0 64 7/27 M24256-B, M24128-B Figure 6. Write Mode Sequences with WC=1 (data write inhibited) WC ACK BYTE WRITE DEV SEL ACK ACK NO ACK DATA IN BYTE ADDR R/W BYTE ADDR START WC ACK PAGE WRITE DEV SEL ACK ACK NO ACK DATA IN 1 DATA IN 2 BYTE ADDR R/W BYTE ADDR WC (cont'd) NO ACK PAGE WRITE (cont'd) NO ACK START DATA IN N STOP STOP AI01120C Write Operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 7., and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write instruction with Write Control (WC) driven High (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 6.. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 3.) is sent first, followed by the Least Significant Byte (Table 4.). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the "10 th bit" time slot), either at the end of a Byte Write or a Page 8/27 Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition, the delay tW, and the successful completion of a Write operation, the device's internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. Byte Write After the Device Select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7.. M24256-B, M24128-B Page Write The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided that they are all located in the same 'row' in the memory: that is, the most significant memory address bits (b14-b6 for M24256-B, and b13-b6 for M24128-B) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `rollover' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 6 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. Figure 7. Write Mode Sequences with WC=0 (data write enabled) WC ACK BYTE WRITE DEV SEL ACK ACK DATA IN ACK BYTE ADDR R/W BYTE ADDR START WC ACK PAGE WRITE DEV SEL ACK ACK DATA IN 1 ACK DATA IN 2 BYTE ADDR R/W BYTE ADDR WC (cont'd) START ACK PAGE WRITE (cont'd) DATA IN N ACK STOP STOP AI01106C 9/27 M24256-B, M24128-B Figure 8. Write Cycle Polling Flowchart using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK Returned YES NO Next Operation is Addressing the Memory YES ReSTART Send Address and Receive ACK STOP NO START Condition YES DATA for the WRITE Operation DEVICE SELECT with RW = 1 Continue the WRITE Operation Continue the Random READ Operation AI01847C Minimizing System Delays by Polling On ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 20. and Table 21., but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 8., is: - - - Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). 10/27 M24256-B, M24128-B Figure 9. Read Mode Sequences ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP ACK ACK RANDOM ADDRESS READ START DEV SEL * R/W ACK DEV SEL * START ACK NO ACK DATA OUT STOP ACK BYTE ADDR BYTE ADDR R/W ACK SEQUENTIAL CURRENT READ START DEV SEL R/W ACK ACK NO ACK DATA OUT 1 DATA OUT N STOP ACK SEQUENTIAL RANDOM READ START DEV SEL * ACK ACK DEV SEL * START ACK BYTE ADDR R/W BYTE ADDR DATA OUT 1 R/W ACK NO ACK DATA OUT N STOP AI01105C Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical. Read Operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device's internal address counter is incremented by one, to point to the next byte address. Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 9.) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and out- puts the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 9., without acknowledging the byte. 11/27 M24256-B, M24128-B Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 9.. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). 12/27 M24256-B, M24128-B MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 6. Absolute Maximum Ratings Symbol TSTG TLEAD VIO VCC VESD Storage Temperature Lead Temperature during Soldering Input or Output range Supply Voltage -V voltage range all other voltage ranges -V voltage range all other voltage ranges Parameter Min. -65 Max. 150 Unit C C V V V plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. See note 1 -0.50 -0.50 -0.50 -0.50 -3000 4.2 6.5 4.2 6.5 3000 Electrostatic Discharge Voltage (Human Body model) 2 Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK (R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ) 13/27 M24256-B, M24128-B DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 7. Operating Conditions (M24xxx-B) Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 4.5 -40 Max. 5.5 85 Unit V C ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8. Operating Conditions (M24xxx-BV) Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 2.5 -40 Max. 3.6 85 Unit V C Table 9. Operating Conditions (M24xxx-BW) Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 2.5 -40 Max. 5.5 85 Unit V C Table 10. Operating Conditions (M24128-BR) Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 1.8 -40 Max. 5.5 85 Unit V C Table 11. Operating Conditions (M24256-BS) Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 1.8 -40 Max. 3.6 85 Unit V C Table 12. AC Measurement Conditions Symbol CL Load Capacitance Input Rise and Fall Times Input Levels Input and Output Timing Reference Levels Parameter Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V 14/27 M24256-B, M24128-B Figure 10. AC Measurement I/O Waveform Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC AI00825B 0.2VCC Table 13. Input Parameters Symbol CIN CIN ZL ZH tNS Parameter1,2 Input Capacitance (SDA) Input Capacitance (other pins) Input Impedance (E2, E1, E0, WC) Input Impedance (E2, E1, E0, WC) Pulse width ignored (Input Filter on SCL and SDA) VIN < 0.5 V VIN > 0.7VCC Single glitch 30 500 100 Test Condition Min. Max. 8 6 Unit pF pF k k ns Note: 1. TA = 25C, f = 400kHz 2. Sampled only, not 100% tested. Table 14. M24xxx-BV Power-Up Timing and Vth Threshold Symbol tPU Vth Parameter1 Time delay to Read or Write instruction Threshold Voltage 1.4 Test Condition Min. Max. 200 1.6 Unit s V Note: 1. These parameters are characterized only. Table 15. DC Characteristics (M24xxx-B) Symbol ILI ILO ICC ICC1 Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current Stand-by Supply Current Input Low Voltage (SCL, SDA) VIL Input Low Voltage (E2, E1, E0, WC) Input High Voltage (E2, E1, E0, SCL, SDA, WC) Output Low Voltage IOL = 3 mA, VCC = 5 V Test Condition (in addition to those in Table 7.) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z VCC=5V, fc=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 5 V -0.45 -0.45 0.7VCC Min. Max. 2 2 2 10 0.3VCC 0.5 VCC+1 0.4 Unit A A mA A V V V V VIH VOL 15/27 M24256-B, M24128-B Table 16. DC Characteristics (M24xxx-BV) Symbol ILI ILO ICC ICC1 Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current Stand-by Supply Current Input Low Voltage (SCL, SDA) VIL Input Low Voltage (E2, E1, E0, WC) Input High Voltage (E2, E1, E0, SCL, SDA, WC) Output Low Voltage IOL = 2.1 mA, VCC = 2.7 V Test Condition (in addition to those in Table 8.) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z VCC =2.7V, fc=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 2.7 V -0.45 -0.45 0.7VCC Min. Max. 2 2 2 2 0.3VCC 0.5 VCC+0.6 0.4 Unit A A mA A V V V V VIH VOL Table 17. DC Characteristics (M24xxx-BW) Symbol ILI ILO ICC ICC1 Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current Stand-by Supply Current Input Low Voltage (SCL, SDA) VIL Input Low Voltage (E2, E1, E0, WC) Input High Voltage (E2, E1, E0, SCL, SDA, WC) Output Low Voltage IOL = 2.1 mA, VCC = 2.5 V Test Condition (in addition to those in Table 9.) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z VCC =2.5V, fc=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 2.5 V -0.45 -0.45 0.7VCC Min. Max. 2 2 1 2 0.3VCC 0.5 VCC+1 0.4 Unit A A mA A V V V V VIH VOL 16/27 M24256-B, M24128-B Table 18. DC Characteristics (M24128-BR) Symbol ILI ILO ICC ICC1 Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current Stand-by Supply Current Input Low Voltage (SCL, SDA) VIL Input Low Voltage (E2, E1, E0, WC) Input High Voltage (E2, E1, E0, SCL, SDA, WC) Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V Test Condition (in addition to those in Table 10.) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z VCC =1.8V, fc=100kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 1.8 V -0.45 -0.45 0.7VCC Min. Max. 2 2 0.8 1 0.3 VCC 0.5 VCC+1 0.2 Unit A A mA A V V V V VIH VOL Table 19. DC Characteristics (M24256-BS) Symbol ILI ILO ICC ICC1 Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current Stand-by Supply Current Input Low Voltage (SCL, SDA) VIL Input Low Voltage (E2, E1, E0, WC) Input High Voltage (E2, E1, E0, SCL, SDA, WC) Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V Test Condition (in addition to those in Table 11.) VIN = VSS or VCC device in Stand-by mode VOUT = VSS or VCC, SDA in Hi-Z VCC =1.8V, fc=400kHz (rise/fall time < 30ns) VIN = VSS or VCC , VCC = 1.8 V -0.45 -0.45 0.7VCC Min. Max. 2 2 0.8 1 0.3 VCC 0.5 VCC+0.6 0.2 Unit A A mA A V V V V VIH VOL 17/27 M24256-B, M24128-B Table 20. AC Characteristics (M24xxx-B, M24xxx-BW) Test conditions specified in Table 12. and Table 7. or Table 9. Symbol fC tCHCL tCLCH tCH1CH2 tCL1CL2 tDH1DH2 2 tDL1DL2 2 tDXCX tCLDX tCLQX tCLQV 3 tCHDX 1 tDLCL tCHDH tDHDL tW Note: 1. 2. 3. 4. Alt. fSCL tHIGH tLOW tR tF tR tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Clock Frequency Parameter Min. Max. 400 Unit kHz ns ns Clock Pulse Width High Clock Pulse Width Low Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Data In Set Up Time Data In Hold Time Data Out Hold Time Clock Low to Next Data Valid (Access Time) Start Condition Set Up Time Start Condition Hold Time Stop Condition Set Up Time Time between Stop Condition and Next Start Condition Write Time 600 1300 300 300 20 20 100 0 200 200 600 600 600 1300 10 or 4 5 900 300 300 ns ns ns ns ns ns ns ns ns ns ns ns ms For a reSTART condition, or following a Write cycle. Sampled only, not 100% tested. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. The Write Time of 5 ms only applies to M24128-B and M24128-BW devices bearing the process letter "B" in the package marking (on the top side of the package, on the right side), otherwise the Write Time is 10 ms. For further details, please contact your nearest ST sales office, and ask for a copy of the M24128 Product Change Notice. 18/27 M24256-B, M24128-B Table 21. AC Characteristics (M24xxx-BV, M24128-BR, M24256-BS) Test conditions specified in Table 12. and Table 8. or Table 10. or Table 11. Symbol fC tCHCL tCLCH tCH1CH2 tCL1CL2 tDH1DH2 2 tDL1DL2 2 tDXCX tCLDX tCLQX tCLQV 3 tCHDX 1 tDLCL tCHDH tDHDL tW Alt. fSCL tHIGH tLOW tR tF tR tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Clock Frequency Clock Pulse Width High Clock Pulse Width Low Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Data In Set Up Time Data In Hold Time Data Out Hold Time Clock Low to Next Data Valid (Access Time) Start Condition Set Up Time Start Condition Hold Time Stop Condition Set Up Time Time between Stop Condition and Next Start Condition Write Time 20 20 100 0 200 200 600 600 600 1300 10 900 600 1300 300 300 300 300 Parameter Min. Max. 400 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Note: 1. For a reSTART condition, or following a Write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 19/27 M24256-B, M24128-B Figure 11. AC Waveforms tCHCL tCLCH SCL tDLCL SDA In tCHDX START Condition SDA Input tCLDX SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition SCL SDA In tCHDH STOP Condition tW Write Cycle tCHDX START Condition SCL tCLQV SDA Out Data Valid tCLQX AI00795C 20/27 M24256-B, M24128-B PACKAGE MECHANICAL Figure 12. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline b2 A2 A1 b e A L E c eA eB D 8 E1 1 PDIP-B Note: Drawing is not to scale. Table 22. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data mm Symb. Typ. A A1 A2 b b2 c D E E1 e eA eB L 3.30 2.92 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 - - 4.95 0.56 1.78 0.36 10.16 8.26 7.11 - - 10.92 3.81 0.130 0.115 0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300 Min. Max. 5.33 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 - - 0.195 0.022 0.070 0.014 0.400 0.325 0.280 - - 0.430 0.150 Typ. Min. Max. 0.210 inches 21/27 M24256-B, M24128-B Figure 13. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline h x 45 A C B e D CP N E 1 H A1 L SO-a Note: Drawing is not to scale. Table 23. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data mm Symb. Typ. A A1 B C D E e H h L 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches N CP 22/27 M24256-B, M24128-B Figure 14. SO8 wide - 8 lead Plastic Small Outline, 200 mils body width, Package Outline A2 B e D A C CP N E 1 H A1 L SO-b Note: Drawing is not to scale. Table 24. SO8 wide - 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data mm Symb. Typ. A A1 A2 B C D E e H L 1.27 0.20 0.35 - 5.15 5.20 - 7.70 0.50 0 8 0.10 0.10 Min. Max. 2.03 0.25 1.78 0.45 - 5.35 5.40 - 8.10 0.80 10 0.050 0.008 0.014 - 0.203 0.205 - 0.303 0.020 0 8 0.004 0.004 Typ. Min. Max. 0.080 0.010 0.070 0.018 - 0.211 0.213 - 0.319 0.031 10 inches N CP 23/27 M24256-B, M24128-B Figure 15. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline D 8 5 c E1 E 1 4 A1 A CP b e A2 L L1 TSSOP8AM Note: Drawing is not to scale. Table 25. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data mm Symbol Typ. A A1 A2 b c CP D e E E1 L L1 3.000 0.650 6.400 4.400 0.600 1.000 0 8 2.900 - 6.200 4.300 0.450 1.000 0.050 0.800 0.190 0.090 Min. Max. 1.200 0.150 1.050 0.300 0.200 0.100 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295 inches 24/27 M24256-B, M24128-B PART NUMBERING Table 26. Ordering Information Scheme Example: Device Type M24 = I2C serial access EEPROM Device Function 256 = 256 Kbit (32K x 8) 128 = 128 Kbit (16K x 8) Operating Voltage blank3 = VCC = 4.5 to 5.5V V1 = VCC = 2.5 to 3.6V W3 = VCC = 2.5 to 5.5V R2 = VCC = 1.8 to 5.5V S1 = VCC = 1.8 to 3.6V Package BN = PDIP8 MN = SO8 (150 mil width) MW = SO8 (200 mil width) DW = TSSOP8 (169 mil width) Device Grade 6 = Industrial: device tested with standard test flow over -40 to 85 C Option blank = Standard Packing T = Tape & Reel Packing Plating Technology blank = Standard SnPb plating P = Lead-Free and RoHS compliant G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free Note: 1. Available for the M24256-B only. 2. Available for the M24128-B only. 3. M24256-B and M24256-BW bearing the process letter "V" in the package marking, and M24128-B and M24128-BW bearing the process letter "B" in the package marking (on the top side of the package, on the right side), guarantee more than 1 million Erase/ Write cycle endurance. For more information about these devices, and their device identification, please contact your nearest ST sales office, and ask for the Product Change Notice. M24256 - B W MN 6 T P For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 25/27 M24256-B, M24128-B REVISION HISTORY Table 27. Document Revision History Date 28-Dec-1999 24-Feb-2000 22-Nov-2000 Rev. 2.1 2.2 2.3 TSSOP8 package added E2, E1, E0 must be tied to Vcc or Vss Low Pass Filter Time Constant changed to Glitch Filter -V voltage range added -V voltage range changed to 2.5V to 3.6V Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated. SO8(wide) package added References to PSDIP8 changed to PDIP8, and Package Mechanical data updated -R voltage range added. Package mechanical data updated for TSSOP8 and TSSOP14 packages according to JEDEC\MO-153 Document promoted from "Preliminary Data" to "Full Data Sheet" TSSOP14 package removed Absolute Max Ratings and DC characteristics updated for M24256-BV Specification of Test Condition for Leakage Currents in the DC Characteristics table improved 1 million Erase/Write cycle endurance for M24256-B and M24256-BW products with process letter "V" Document reformatted. Parameters changed are: 1 million Erase/Write cycle endurance and 5 ms write time for M24128-B and M24128-BW products with process letter "B". Superfluous (and incorrectly present) 100kHz AC Characteristics table for M24256-BR removed. Initial delivery state specified. -R and -S ranges are no longer Preliminary Data. Package mechanical data for unavailable package removed. Table of contents, and Pb-free options added. Minor wording changes in Summary Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations. VIL(min) improved to -0.45V. SO8W package added. Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified Description of Revision 30-Jan-2001 2.4 01-Jun-2001 2.5 16-Oct-2001 09-Nov-2001 21-Mar-2002 18-Oct-2002 20-Nov-2002 02-Jun-2003 2.6 2.7 2.8 3.0 3.1 3.2 22-Oct-2003 4.0 16-Apr-2004 5.0 26/27 M24256-B, M24128-B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 27/27 |
Price & Availability of M24128-BWBN6
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |